The 74HC595 is an 8-bit
serial-in/serial or parallel-out shift register with a storage register and
3-state outputs. Both the shift and storage register have separate clocks. The
device features a serial input (DS) and a serial output (Q7S) to enable
cascading and an asynchronous reset MR input. A LOW on MR will reset the shift
register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The
data in the shift register is transferred to the storage register on a
LOW-to-HIGH transition of the STCP input.
If both clocks are connected together,
the shift register will always be one clock pulse ahead of the storage
register. Data in the storage register appears at the output whenever the
output enable input (OE) is LOW. A HIGH on OE causes the outputs to assume a
high-impedance OFF-state. Operation of the OE input does not affect the state
of the registers. Inputs include clamp diodes. This enables the use of current
limiting resistors to interface inputs to voltages in excess of VCC.
SN74HC595N 74HC595 8-Bit Shift
Register with Output Latches and Eight 3-State Outputs, DIP 16, Cascadable.
Features
·
8-bit,
Serial In – Parallel out Shift register
·
Operating
Voltage: 2V to 6V
·
Power
Consumption: 80uA
·
Output
source/sink current: 35mA
·
Output
Voltage is equal to Operating voltage
·
Minimum
high-level Input Voltage: 3.15V @(Vcc=4.5V)
·
Maximum
low-level Input Voltage: 1.35V @(Vcc=4.5V)
·
Can
be easily cascaded with more IC to get more outputs
·
Maximum
Clock Frequency: 25Mhz @4.5V
·
Available
in 16-pin PDIP, GDIP, PDSO packages
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